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d a t a sh eet preliminary speci?cation supersedes data of 1996 feb 28 file under integrated circuits, ic02 1997 mar 11 integrated circuits TDA9852 i 2 c-bus controlled btsc stereo/sap decoder and audio processor
1997 mar 11 2 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 features quasi alignment-free application due to automatic adjustment of channel separation via i 2 c-bus high integration level with automatically tuned integrated filters input level adjustment i 2 c-bus controlled alignment-free sap processing dbx noise reduction circuit power supply i 2 c-bus transceiver. stereo decoder stereo pilot pll circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via i 2 c-bus. audio processor selector for internal and external signals (line in) automatic volume level control (control range +6 to - 15 db) interface for external noise reduction circuits volume control (control range +16 to - 71 db) special loudness characteristic automatically controlled in combination with volume setting (control range 28 db) audio signal zero crossing detection between any volume step switching mute control at audio signal zero crossing mute control via i 2 c-bus. general description the TDA9852 is a bipolar-integrated btsc stereo decoder with hi-fi audio processor (i 2 c-bus controlled) for application in tv sets, vcrs and multimedia. ordering information type number package name description version TDA9852 sdip42 plastic shrink dual in-line package; 42 leads (600 mil) sot270-1 TDA9852h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2
1997 mar 11 3 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 license information a license is required for the use of this product. for further information, please contact quick reference data company branch address that corporation licensing operations 734 forest st. marlborough, ma 01752 usa tel.: (508) 229-2500 fax: (508) 229-2590 tokyo of?ce 405 palm house, 1-20-2 honmachi shibuya-ku, tokyo 151 japan tel.: (03) 3378-0915 fax: (03) 3374-5191 symbol parameter conditions min. typ. max. unit v cc supply voltage 8.0 8.5 9.0 v i cc supply current - 75 95 ma v comp(rms) input signal voltage (rms value) 100% modulation l + r; f i = 300 hz - 250 - mv v or,l(rms) output signal voltage (rms value) 100% modulation l + r; f i = 300 hz - 500 - mv g la input level adjustment control - 3.5 - +4.0 db a cs stereo channel separation f l = 300 hz; f r = 3 khz 25 35 - db thd l,r total harmonic distortion l + r f i = 1 khz - 0.2 - % v i, o(rms) signal handling (rms value) thd < 0.5% 2 -- v avl control range - 15 - +6 db g c volume control range - 71 - +16 db l b maximum loudness boost f i =40hz - 17 - db s/n signal-to-noise ratio line out (mono); v o = 0.5 v (rms) ccir noise weighting filter (peak value) - 60 - db din noise weighting filter (rms value) - 73 - dba s/n signal-to-noise ratio audio section; v o = 2 v (rms); gain = 0 db ccir noise weighting filter (peak value) - 94 - db din noise weighting filter (rms value) - 107 - dba
1997 mar 11 4 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 block diagram handbook, full pagewidth stereo adjust sap demodulator input level adjust comp stereo/ sap switch dematrix + lineout select dbx r6 r7 logic i 2 c transceiver sda scl stereo decoder ceramic resonator murata csb503f58 mha309 lol lil external input right (eir) external input left (eil) agnd dgnd lor lir input select automatic volume and level control effects volume right loudness control out right zero crossing volume left loudness control out left supply vil vir TDA9852 outr r3 r2 c11 c8 c28 c6 c7 c9 c12 c10 40 (36) 39 (35) 38 (34) 37 (33) 5 (44) c20 32 (28) 33 (29) 36 (32) 34 (30) 35 (31) c16 q1 31 (27) 41 (37) r5 r4 c29 c14 c30 (42) 3 (43) 4 (17) 21 20 (15) (16) (39) (1) 6 (3) 8 (4) 9 (2) 7 (21) 25 (19) 23 c15 c49 v cc c47 c26 c34 (8) 13 (9) 14 c22 (12) 17 (13) 18 (14) 19 26 (22) 27 (23) 28 (24) 29 (25) 30 (26) c2 c3 c4 c5 r1 (20) 24 (10) 15 (11) 16 c19 c18 c17 c1 c21 c23 (6) 11 (5) 10 (7) 12 c24 c25 c27 (18) 22 (41) 2 n.c. (40) 1 (38) 42 outl fig.1 block diagram. the numbers given in parenthesis refer to the TDA9852h version.
1997 mar 11 5 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 component list electrolytic capacitors 20%; foil or ceramic capacitors 10%; resistors 5%; unless otherwise speci?ed; see fig.1. components value type remark c1 10 m f electrolytic 63 v c2 470 nf foil c3 4.7 m f electrolytic 63 v c4 220 nf foil c5 10 m f electrolytic 63 v; i leak < 1.5 m a c6 2.2 m f electrolytic 16 v c7 2.2 m f electrolytic 63 v c8 15 nf foil 5% c9 15 nf foil 5% c10 2.2 m f electrolytic 16 v c11 8.2 nf foil or ceramic 5% smd 2220/1206 c12 150 nf foil 5% c14 150 nf foil 5% c15 100 m f electrolytic 16 v c16 4.7 m f electrolytic 63 v c17 4.7 m f electrolytic 63 v c18 100 nf foil c19 10 m f electrolytic 63 v c20 4.7 m f electrolytic 63 v c21 47 nf foil 5% c22 1 m f electrolytic 63 v c23 1 m f electrolytic 63 v c24 10 m f electrolytic 63 v 10% c25 10 m f electrolytic 63 v 10% c26 2.2 m f electrolytic 16 v c27 2.2 m f electrolytic 63 v c28 4.7 m f electrolytic 63 v 10% c29 2.2 m f electrolytic 16 v c30 8.2 nf foil or ceramic 5% smd 2220/1206 c34 100 m f electrolytic 16 v c47 220 m f electrolytic 25 v c49 100 nf foil or ceramic smd 1206 r1 2.2 k w- r2 20 k w- r3 2.2 k w- r4 20 k w- r5 2.2 k w- r6 8.2 k w- 2%
1997 mar 11 6 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 pinning r7 160 w- 2% q1 csb503f58 radial leads csb503jf958 alternative as smd symbol pins description sdip42 qfp44 outl 1 40 output, left channel ldl 2 41 input loudness, left channel vil 3 42 input volume, left channel eol 4 43 output effects, left channel c av 5 44 automatic volume control capacitor v ref 6 1 reference voltage 0.5v cc lil 7 2 input line control, left channel avl 8 3 input automatic volume control, left channel sol 9 4 output selector, left channel lol 10 5 output line control, left channel c tw 11 6 capacitor timing wideband for dbx c ts 12 7 capacitor timing spectral for dbx c w 13 8 capacitor wideband for dbx c s 14 9 capacitor spectral for dbx veo 15 10 variable emphasis output for dbx vei 16 11 variable emphasis input for dbx c nr 17 12 capacitor noise reduction for dbx c m 18 13 capacitor mute for sap c dec 19 14 capacitor dc-decoupling for sap gnd 20 - ground agnd - 15 analog ground dgnd - 16 digital ground sda 21 17 serial data input/output (i 2 c-bus) scl 22 18 serial clock input (i 2 c-bus) v cc 23 19 supply voltage comp 24 20 composite input signal v cap 25 21 capacitor for electronic ?ltering of supply c p1 26 22 capacitor for pilot detector c p2 27 23 capacitor for pilot detector c ph 28 24 capacitor for phase detector c adj 29 25 capacitor for ?lter adjustment cer 30 26 ceramic resonator c mo 31 27 capacitor dc-decoupling mono components value type remark
1997 mar 11 7 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 c ss 32 28 capacitor dc-decoupling stereo/sap lor 33 29 output line control, right channel sor 34 30 output selector, right channel avr 35 31 input automatic volume control, right channel lir 36 32 input line control, right channel c ps2 37 33 capacitor 2 pseudo function c ps1 38 34 capacitor 1 pseudo function eor 39 35 output effects, right channel vir 40 36 input volume, right channel ldr 41 37 input loudness, right channel outr 42 38 output, right channel n.c. - 39 not connected symbol pins description sdip42 qfp44 fig.2 pin configuration (qfp-version). handbook, full pagewidth TDA9852h mha696 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 v ref lil c av eol vil ldl outl n.c. outr ldr c ps2 lir avr sor lor c ss c adj c ph c p2 c p1 c dec c m c nr v cap comp v cc scl sda dgnd agnd cer c mo vir eor c ps1 sol avl lol c tw c w c s c ts veo vei
1997 mar 11 8 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 fig.3 pin configuration (sdip-version). handbook, halfpage TDA9852 mha310 1 2 42 41 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 outl ldl vil eol c av v ref lil avl sol lol c tw c ts c w c s veo vei c nr c m c dec gnd sda outr ldr vir eor c ps1 c ps2 lir avr sor lor c ss c mo cer c adj c ph c p2 c p1 v cap comp v cc scl functional description stereo decoder i nput level adjustment the composite input signal is fed to the input level adjustment stage. the control range is from - 3.5 to +4.0 db in steps of 0.5 db. the subaddress control 3 of tables 5 and 6 and the level adjust setting of table 21 allows an optimum signal adjustment during the set alignment. the maximum input signal voltage is 2 v (rms). s tereo decoder the output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 khz. the composite signal is then fed into a pilot detector/pilot cancellation circuit and into the mpx demodulator. the main l + r signal passes a 75 m s fixed de-emphasis filter and is fed into the dematrix circuit. the decoded sub-signal l - r is sent to the stereo/sap switch. to generate the pilot signal the stereo demodulator uses a pll circuit including a ceramic resonator. the stereo channel separation is adjusted by an automatic procedure to be performed during set production. for a detailed description see section adjustment procedure. the stereo identification can be read by the i 2 c-bus (see table 2). two different pilot thresholds (data sts = 1; sts = 0) can be selected via the i 2 c-bus (see table 19). sap demodulator the composite signal is fed from the output of the input level adjustment stage to the sap demodulator circuit through a 5f h (f h = horizontal frequency) band-pass filter. the demodulator level is automatically controlled. the sap demodulator includes internal noise and field strength detectors that mute the sap output in the event of insufficient signal conditions. the sap identification signal can be read by the i 2 c-bus (see table 2). s witch the stereo/sap switch feeds either the l - r signal or the sap demodulator output signal via the internal dbx noise reduction circuit to the dematrix/switching circuit. table 12 shows the different switch modes provided at the output pins lor and lol.
1997 mar 11 9 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 dbx decoder the circuit includes all blocks required for the noise reduction system in accordance with the btsc system specification. the output signal is fed through a 73 m s fixed de-emphasis circuit to the dematrix block. i ntegrated filters the filter functions necessary for stereo and sap demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. the required filter accuracy is attained by an automatic filter alignment circuit. audio processor s elector the selector allows selecting either the internal line out signals lor or lol (dematrix output) or the external line in signals lir and lil and combines the left and right signals in several modes (see tables 5 and 6 for subaddress and table 11 for data). the input signal capability of the line inputs (lir/lil) is 2 v (rms). the output of the selector is ac-coupled to the automatic volume level control circuit via pins sor/sol and avr/avl to avoid offset voltages. a utomatic volume level control the automatic volume level stage controls its output voltage to a constant level of typically 200 mv (rms) from an input voltage range of 0.1 to 1.1 v (rms). the circuit adjusts variations in modulation during broadcasting and due to changes in the programme material. the function can be switched off . to avoid audible plops during the permanent operation of the avl circuit a soft blending scheme has been applied between the different gain stages. a capacitor (4.7 m f) at pin c av determines the attack and decay time constants. in addition the ratio of attack and decay time can be changed via i 2 c-bus (see table 15). at power on , the discharged 4.7 m f capacitor at c av must be loaded by the internal decay current. if avl is chosen, this would result in an attenuated avl gain for about 10 seconds after power on . this can be speeded up by choosing via i 2 c-bus an increased charge current (about 10 times higher) for about the first 2 seconds after power on (see table 6, ccd bit in control 1 and table 18). e ffects the audio processor section offers the following mode selections: linear stereo, pseudo stereo, spatial stereo and forced mono.the spatial mode provides an antiphase crosstalk of 30% or 52% (switchable via i 2 c-bus; see table 10). v olume / loudness the volume control range is from +16 db to - 71 db in steps of 1 db and ends with a mute step (see table 8). balance control is achieved by the independent volume control of each channel. the volume control blocks operate in combination with the loudness control. the filter is linear when maximum gain for volume control is selected. the filter characteristic changes automatically over a range of 28 db down to a setting of - 12 db. at - 12 db volume control the maximum loudness boost is obtained. the filter characteristic is determined by external components. the proposed application provides a maximum boost of 17 db for bass and 4.5 db for treble. the loudness may be switched on or off via i 2 c-bus control (see table 9). the left and right volume control stages include two independent zero crossing detectors. a change in volume is automatically activated but not executed. the execution is enabled at the next zero crossing of the signal. if a new volume step is activated before the previous one has been processed, the previous value will be executed first, and then the new value will be activated. if no zero crossing occurs the next volume transmission will enforce the last activated volume setting. the zero crossing is realized between adjoining steps and between any steps, but not from any step to mute. in this case the gmu bit is needed to use. in case only one channel has to be muted, two steps are necessary. the first step is a transmission of any step to - 71 db and the second step is the - 71 db step to mute mode. the step of - 71 db to mute mode has no zero crossing but this is not relevant.
1997 mar 11 10 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 m ute the mute function can be activated independently with last step of volume control at the left or right output. by setting the general mute bit gmu via the i 2 c-bus all outputs are muted. all channels include an independent zero cross detector. the zero crossing mute feature can be selected via bit tzcm: tzcm = 0: forced mute with direct execution tzcm = 1: execution in time with signal zero crossing. in the zero cross mode a change in the gmu polarity is activated but not executed. the execution is enabled at the next zero crossing of the signal. to avoid a large delay of mute switching, when very low frequencies are processed, or the output signal amplitude is lower than the dc offset voltage, the following i 2 c-bus transmissions are needed: a first transmission for mute execution a second transmission about 100 ms later, which must switch the zero crossing mode to forced mute (tzcm = 0) a third transmission to reactivate the zero crossing mode (tzcm = 1). this transmission can take place immediately, but must follow before the next mute execution. adjustment procedure c omposite input level adjustment feed in from fm demodulator the composite signal with 100% modulation (25 khz deviation) l + r; f i = 300 hz. set input level control via i 2 c-bus monitoring line out (500 mv 20 mv). store the setting in a non-volatile memory. a utomatic adjustment procedure capacitors of external inputs lil and lir must be grounded at eil and eir composite input signal l = 300 hz, r = 3.1 khz, 14% modulation for each channel; volume gain +16 db via i 2 c-bus effects, avl, loudness off . line out setting bits: stereo = 1, sap = 0 (see table 12) selector setting sc0, sc1, sc2 = 0, 0, 0 (see table 11) start adjustment by transmission adj = 1 in register ali3; the decoder will align itself after 1 second minimum stop alignment by transmitting adj = 0 in register ali3 read the alignment data by an i 2 c-bus read operation from alr1 and alr2 (see chapter i 2 c-bus protocol) and store it in a non-volatile memory; the alignment procedure overwrites the previous data stored in ali1 and ali2 disconnect the capacitors of external inputs from ground. m anual adjustment manual adjustment is necessary when no dual tone generator is available (e.g. for service). spectral and wideband data have to be set to 10000 (middle position for adjustment range) composite input l = 300 hz; 14% modulation adjust channel separation by varying wideband data composite input l = 3 khz; 14% modulation adjust channel separation by varying spectral data iterative spectral/wideband operation for optimum adjustment store data in non-volatile memory. t iming current for release rate due to possible internal and external spreading, the timing current can be adjusted via i 2 c-bus, see table 20, as recommended by dbx.
1997 mar 11 11 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 requirements for the composite input signal to ensure correct system performance notes 1. low-ohmic preferred, otherwise the signal loss and spreading at comp, caused by z o and the composite input impedance (see chapter characteristics, section input level adjustment control) must be taken into account. 2. in order to prevent clipping at over-modulation (maximum deviation in the btsc system for 100% modulation is 73 khz). 3. for example colour bar or flat field white; 100% video modulation. symbol parameter conditions min. typ. max. unit comp l+r(rms) composite input level for 100% modulation l + r; 25 khz deviation; f i = 300 hz; rms value measured at comp 162 250 363 mv d comp composite input level spreading under operating conditions t amb = - 20 to +70 c; aging; power supply in?uence - 0.5 - +0.5 db z o output impedance note 1 - low-ohmic 5 k w f lf low frequency roll-off 25 khz deviation l + r; - 2db -- 5hz f hf high frequency roll-off 25 khz deviation l + r; - 2 db 100 -- khz thd l,r total harmonic distortion l + r f i = 1 khz; 25 khz deviation -- 0.5 % f i = 1 khz; 125 khz deviation; note 2 -- 1.5 % s/n signal-to-noise ratio l + r/noise ccir 468-2 weighted quasi peak; l + r; 25 khz deviation; f i = 1 khz; 75 m s de-emphasis critical picture modulation; note 3 44 -- db with sync only 54 -- db a sb side band suppression mono into unmodulated sap carrier; sap carrier/side band mono signal: 25 khz deviation, f i = 1 khz; side band: sap carrier frequency 1 khz 46 -- db a sp spectral spurious attenuation l + r/spurious 50 hz to 100 khz; mainly n f h ; no de-emphasis; l + r; 25 khz deviation, f = 1 khz as reference n = 1, 5 35 -- db n = 4, 6 40 -- db n = 2, 3 26 -- db
1997 mar 11 12 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. human body model: c = 100 pf; r = 1.5 k w ; v = 2 kv; charge device model: c = 200 pf; r = 0 w ; v = 300 v. thermal characteristics symbol parameter min. max. unit v cc supply voltage 0 9.5 v v n voltage of all other pins to pin v cc 0v cc v t amb operating ambient temperature - 20 +70 c t stg storage temperature - 65 +150 c v es electrostatic handling; note 1 symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air sot270-1 43 k/w sot307-2 60 k/w
1997 mar 11 13 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 characteristics all voltages are measured relative to gnd; v cc = 8.5 v; r s = 600 w ; r l =10k w ; c l = 2.5 nf; ac-coupled; f i = 1 khz; t amb =25 c; gain control g v = 0 db; balance in mid position; loudness off ; see fig.1; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit general v cc supply voltage 8.0 8.5 9.0 v i cc supply current - 75 95 ma v ref internal reference voltage at pin v ref - 4.25 - v input level adjustment control g la input level adjustment control - 3.5 - +4.0 db g step step resolution - 0.5 - db v i(rms) maximum input voltage level (rms value) 2 -- v z i input impedance 29.5 35 40.5 k w stereo decoder mpx l+r(rms) input voltage level for 100% modulation l + r; 25 khz deviation (rms value) input level adjusted via i 2 c-bus (l + r; f i = 300 hz); monitoring line out - 250 - mv mpx l - r input voltage level for 100% modulation l - r; 50 khz deviation (peak value) - 707 - mv mpx (max) maximum headroom for l + r, l, r f mod < 15 khz; thd < 15% 9 -- db mpx pilot(rms) nominal stereo pilot voltage level (rms value) - 50 - mv st on(rms) pilot threshold voltage stereo on (rms value) data sts = 1 -- 35 mv data sts = 0 -- 30 mv st off(rms) pilot threshold voltage stereo off (rms value) data sts = 1 15 -- mv data sts = 0 10 -- mv hys hysteresis - 2.5 - db out l+r output voltage level for 100% modulation l + r at line out input level adjusted via i 2 c-bus (l + r; f i = 300 hz); monitoring line out 480 500 520 mv a cs stereo channel separation l/r at line out aligned with dual tone 14% modulation for each channel; see section adjustment procedure in chapter functional description f l = 300 hz; f r = 3 khz 25 35 - db f l = 300 hz; f r = 8 khz 20 30 - db f l = 300 hz; f r = 10 khz 15 25 - db
1997 mar 11 14 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 f l, r l, r frequency response 14% modulation; f ref = 300 hz l or r f i =50hzto10khz - 3 -- db f i = 12 khz -- 3 - db thd l,r total harmonic distortion l, r at line out modulation l or r 1% to 100%; f i = 1 khz - 0.2 1.0 % s/n signal-to-noise ratio mono mode; ccir 468-2 weighted; quasi peak; 500 mv output signal 50 60 - db stereo decoder, oscillator (vcxo); note 1 f o nominal vcxo output frequency (32f h ) with nominal ceramic resonator - 503.5 - khz f of spread of free-running frequency with nominal ceramic resonator 500.0 - 507.0 khz d f h capture range frequency (nominal pilot) 190 265 - hz sap demodulator; note 2 sap i(rms) nominal sap carrier input voltage level (rms value) 15 khz frequency deviation of intercarrier - 150 - mv sap on(rms) threshold voltage sap on (rms value) -- 85 mv sap off(rms) threshold voltage sap off (rms value) 35 -- mv sap hys hysteresis - 2 - db sap lev sap output voltage level at line out mode selector in position sap/sap; f mod = 300 hz; 100% modulation - 500 - mv f res frequency response 14% modulation; 50 hz to 8 khz; f ref = 300 hz - 3 -- db thd total harmonic distortion f i = 1 khz - 0.5 2.0 % symbol parameter conditions min. typ. max. unit
1997 mar 11 15 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 line out at pins lol and lor v o(rms) nominal output voltage (rms value) 100% modulation - 500 - mv head o output headroom 9 -- db z o output impedance - 80 120 w v o dc output voltage 0.45v cc 0.5v cc 0.55v cc v r l output load resistance 5 -- k w c l output load capacitance -- 2.5 nf a ct crosstalk l, r into sap 100% modulation; f i = 1 khz; l or r; mode selector switched to sap/sap 50 75 - db crosstalk sap into l, r 100% modulation; f i = 1 khz; sap; mode selector switched to stereo 50 70 - db d v st-sap output voltage difference if switched from l, r to sap 250 hz to 6.3 khz -- 3db dbx noise reduction circuit t adj stereo adjustment time see section adjustment procedure in chapter functional description -- 1s i s nominal timing current for nominal release rate of spectral rms detector i s can be measured at pin c ts via current meter connected to 1 2 v cc +1v - 24 -m a d i s spread of timing current - 15 - +15 % i s range timing current range 7 steps via i 2 c-bus - 30 - % i t timing current for release rate of wideband rms detector - 1 3 i s -m a rel rate nominal rms detector release rate nominal timing current and external capacitor values wideband - 125 - db/s spectral - 381 - db/s symbol parameter conditions min. typ. max. unit
1997 mar 11 16 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 circuit section from pins lil and lir to pins outl and outr; note 3 b roll-off frequencies c 6 , c 7 , c 10 , c 26 , c 27 and c 29 = 2.2 m f; z i = z i(min) low frequency ( - 3 db) -- 20 hz high frequency ( - 0.5 db) 20 -- khz thd total harmonic distortion v i = 1000 mv; g v = 0 db; avl on - 0.2 0.5 % v i = 2000 mv; g v = 0 db; avl on - 0.2 0.5 % v i = 1000 mv; g v = 0 db; avl off - 0.02 - % v i = 2000 mv; g v = 0 db; avl off - 0.02 - % rr ripple rejection v r(rms) < 200 mv; f i = 100 hz 47 50 - db a ct crosstalk between bus inputs and signal outputs notes 4 and 5 - 110 - db v no noise output voltage ccir 468-2 weighted; quasi peak; avl off ; loudness off ; g v =0db - 40 80 m v measured in dba; avl off ; loudness off ; g v =0db - 8 -m v a cs channel separation v i =1v; f i = 1 khz 75 -- db v i =1v; f i = 12.5 khz 75 -- db effect controls a spat1 anti-phase crosstalk by spatial effect - 52 - % a spat2 - 30 - % j phase shift by pseudo-stereo see fig.4 -- -- symbol parameter conditions min. typ. max. unit
1997 mar 11 17 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 automatic volume level control (avl) z i input impedance 8.8 11.0 13.2 k w v i(rms) maximum input voltage (rms value) thd < 0.2% 2 tbf - v g v gain, maximum boost 5 6 7 db maximum attenuation 14 15 16 db g step equivalent step width between the input stages (soft switching system) - 1.5 - db v iop(rms) input level at maximum boost (rms value) - 0.1 - v input level at maximum attenuation (rms value) - 1.125 - v v o(rms) output level in avl operation (rms value) see fig.5 160 200 250 mv v dc off dc offset between different gain steps voltage at pin c av 6.50 to 6.33 v or 6.33 to 6.11 v or 6.11 to 5.33 v or 5.33 to 2.60 v; note 6 -- 6mv r att discharge resistors for attack time constant at1 = 0; at2 = 0; note 7 340 420 520 w at1 = 1; at2 = 0; note 7 590 730 910 w at1 = 0; at2 = 1; note 7 0.96 1.2 1.5 k w at1 = 1; at2 = 1; note 7 1.7 2.1 2.6 k w i dec charge current for decay time normal mode; ccd = 0; note 8 1.6 2.0 2.4 m a power- on speed-up; ccd = 1; note 8 - tbf -m a selector from pins lol, lor, lil and lir to pins sol and sor z i input impedance 16 20 24 k w a s input isolation of one selected source to the other input v i =1v; f i = 1 khz 86 96 - db v i =1v; f i = 12.5 khz 80 96 - db v i(rms) maximum input voltage (rms value) thd < 0.5% 2 2.3 - v v dc off dc offset voltage at selector output by selection of any inputs -- 25 mv z o output impedance - 80 120 w r l output load resistance 5 -- k w c l output load capacitance 0 - 2.5 nf g v voltage gain, selector - 0 - db symbol parameter conditions min. typ. max. unit
1997 mar 11 18 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 audio control part; input pins vil and vir to pins outx and outs z i volume input impedance 8.0 10.0 12.0 k w z o output impedance - 80 120 w r l output load resistance 5 -- k w c l output load capacitance 0 - 2.5 nf v i(rms) maximum input voltage (rms value) thd < 0.5% 2.0 2.15 - v v no noise output voltage ccir 468-2 weighted; quasi peak g v =16db - 110 220 m v g v =0db - 33 50 m v mute position - 10 -m v g c total continuous control range maximum boost - 16 - db maximum attenuation - 71 - db g step step resolution - 1 - db step error between adjoining step -- 0.5 db d g a attenuator set error g v = +16 to - 50 db -- 2db g v = - 51 to - 71 db -- 3db d g l gain tracking error g v = +16 to - 50 db -- 2db a m mute attenuation 80 -- db v dc off dc step offset between any adjacent step g v = +16 to 0 db - 0.2 10.0 mv g v =0to - 71 db -- 5mv dc step offset between any step to mute g v = +16 to +1 db - 215mv g v =0to - 71 db - 110mv loudness control part l b maximum loudness boost loudness on ; referred to loudness off ; boost is determined by external components; see fig.6 f i =40hz - 17 - db f i = 10 khz - 4.5 - db l g loudness control range - 12 - +16 muting at power supply drop for outr and outs v cc-drop supply drop for mute active - v cap - 0.7 - v power-on reset; note 9 v reset(sta) start of reset voltage increasing supply voltage -- 2.5 v decreasing supply voltage 4.2 5 5.8 v v reset(end) end of reset voltage increasing supply voltage 5.2 6 6.8 v symbol parameter conditions min. typ. max. unit
1997 mar 11 19 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 notes to the characteristics 1. the oscillator is designed to operate together with murata resonator csb503f58. change of the resonator supplier is possible, but the resonator speci?cation must be close to csb503f58. 2. the internal sap carrier level is determined by the composite input level and the level adjustment gain. 3. frequency range 20 hz to 20 khz; select in to input line control; effects: linear stereo. 4. crosstalk: 5. the transmission contains: a) total initialization with mad and sad for volume and 11 data words, see also definition of characteristics b) clock frequency = 50 khz c) repetition burst rate = 400 hz d) maximum bus signal amplitude = 5 v (p-p). 6. the listed pin voltage corresponds with typical gain steps of +6 db, +3 db, 0 db, - 6 db and - 15 db. 7. attack time constant = c av r att . 8. example: c av = 4.7 m f; i dec =2 m a; g 1 = - 9 db; g 2 =+6db ? decay time results in 4.14 s. 9. when reset is active the gmu-bit (general mute) and the lmu-bit (line out mute) is set and the i 2 c-bus receiver is in the reset position. 10. the ac characteristics are in accordance with the i 2 c-bus specification. the maximum clock frequency is 100 khz. information about the i 2 c-bus can be found in the brochure the i 2 c-bus and how to use it (order number 9398 393 40011). digital part (i 2 c-bus pins); note 10 v ih high level input voltage 3 - v cc v v il low level input voltage - 0.3 - +1.5 v i ih high level input current - 10 - +10 m a i il low level input current - 10 - +10 m a v ol low level output voltage i il =3ma -- +0.4 v symbol parameter conditions min. typ. max. unit 20 log v bus(p-p) v o(rms) -------------------- - decay time c av 0.76 v 10 g 1 C 20 ---------- 10 g 2 C 20 ---------- C ? ? ? ?? i dec ------------------------------------------------------------------------------- =
1997 mar 11 20 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 i 2 c-bus protocol i 2 c-bus format to read (slave transmits data) table 1 explanation of i 2 c-bus format to read (slave transmits data) table 2 de?nition of the transmitted bytes after read condition table 3 function of the bits in table 2 the master generates an acknowledge when it has received the first data word alr1, then the slave transmits the next data word alr2. afterwards the master generates an acknowledge, then the slave begins transmitting the first data word alr1 etc. until the master generates no acknowledge and transmits a stop condition. s slave address r/ w a data ma data p name description s start condition; generated by the master standard slave address (mad) 101 101 1 r/ w 1 (read); generated by the master a acknowledge; generated by the slave data slave transmits an 8-bit data word ma acknowledge; generated by the master p stop condition; generated by the master function byte msb lsb d7 d6 d5 d4 d3 d2 d1 d0 alignment read 1 alr1 y sapp stp a14 a13 a12 a11 a10 alignment read 2 alr2 y sapp stp a24 a23 a22 a21 a20 bits function stp stereo pilot identification (stereo received = 1) sapp sap pilot identification (sap received = 1) a1x to a2x stereo alignment read data a1x for wideband expander a2x for spectral expander y indefinite
1997 mar 11 21 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 i 2 c-bus format to write (slave receives data) table 4 explanation of i 2 c-bus format to write (slave receives data) if more than 1 byte of data is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of table 5 is performed. table 5 subaddress second byte after mad note 1. in auto-increment mode it is necessary to insert 3 dummy data words between volume left and control 1. table 6 de?nition of third byte, third byte after mad and sad s slave address r/ w a subaddress a data a p name description s start condition standard slave address (mad) 101 101 1 r/ w 0 (write) a acknowledge; generated by the slave subaddress (sad) see table 5 data see table 6 p stop condition function register msb lsb d7 d6 d5 d4 d3 d2 d1 d0 volume right vr 0 0 0 0 0 0 0 0 volume left vl 0 0 0 0 0 0 0 1 control 1 (note 1) con1 0 0 0 0 0 1 0 1 control 2 con2 0 0 0 0 0 1 1 0 control 3 con3 0 0 0 0 0 1 1 1 alignment 1 ali1 0 0 0 0 1 0 0 0 alignment 2 ali2 0 0 0 0 1 0 0 1 alignment 3 ali3 0 0 0 0 1 0 1 0 function register msb lsb d7 d6 d5 d4 d3 d2 d1 d0 volume right vr 0 vr6 vr5 vr4 vr3 vr2 vr1 vr0 volume left vl 0 vl6 vl5 vl4 vl3 vl2 vl1 vl0 control 1 con1 gmu avlon loff ccd 0 sc2 sc1 sc0 control 2 con2 sap stereo tzcm 1 lmu ef2 ef1 ef0 control 3 con3 0 0 0 0 l3 l2 l1 l0 alignment 1 ali1 0 0 0 a14 a13 a12 a11 a10 alignment 2 ali2 sts 0 0 a24 a23 a22 a21 a20 alignment 3 ali3 adj at1 at2 0 1 tc2 tc1 tc0
1997 mar 11 22 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 table 7 function of the bits in table 6 table 8 volume setting bits function vr0 to vr6 volume control right vl0 to vl6 volume control left gmu mute control for all outputs (generate mute) avlon avl on / off ccd increased avl decay current on / off loff switch loudness on / off sc0 to sc2 selection between line in and line out stereo, sap mode selection for line out tzcm zero cross mode in mute operation (right and left output stage) lmu mute control for line out ef0 to ef2 selection between mono, stereo linear, spatial stereo and pseudo mode l0 to l3 input level adjustment adj stereo adjustment on / off a1x to a2x stereo alignment data a1x for wideband expander a2x for spectral expander at1 and at2 attack time at avl tc0 to tc2 timing current alignment data sts stereo level switch function g v (db) data v6 v5 v4 v3 v2 v1 v0 161111111 151111110 141111101 131111100 121111011 111111010 101111001 91111000 81110111 71110110 61110101 51110100 41110011 31110010 21110001 11110000
1997 mar 11 23 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 01101111 - 11101110 - 21101101 - 31101100 - 41101011 - 51101010 - 61101001 - 71101000 - 81100111 - 91100110 - 101100101 - 111100100 - 121100011 - 131100010 - 141100001 - 151100000 - 161011111 - 171011110 - 181011101 - 191011100 - 201011011 - 211011010 - 221011001 - 231011000 - 241010111 - 251010110 - 261010101 - 271010100 - 281010011 - 291010010 - 301010001 - 311010000 - 321001111 - 331001110 - 341001101 - 351001100 - 361001011 - 371001010 - 381001001 function g v (db) data v6 v5 v4 v3 v2 v1 v0
1997 mar 11 24 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 - 391001000 - 401000111 - 411000110 - 421000101 - 431000100 - 441000011 - 451000010 - 461000001 - 471000000 - 480111111 - 490111110 - 500111101 - 510111100 - 520111011 - 530111010 - 540111001 - 550111000 - 560110111 - 570110110 - 580110101 - 590110100 - 600110011 - 610110010 - 620110001 - 630110000 - 640101111 - 650101110 - 660101101 - 670101100 - 680101011 - 690101010 - 700101001 - 710101000 mute 0 1 0 0 1 1 1 function g v (db) data v6 v5 v4 v3 v2 v1 v0
1997 mar 11 25 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 table 9 loudness setting table 10 effects setting characteristic data loff with loudness 0 linear 1 function data ef2 ef1 ef0 stereo linear on 000 pseudo on 001 spatial stereo; 30% anti-phase crosstalk 010 spatial stereo; 50% anti-phase crosstalk 011 forced mono 1 1 1 table 11 selector setting note 1. input connected to outputs sor and sol. function (1) data sc2 sc1 sc0 inputs lor and lol 0 0 0 inputs lor and lor 0 0 1 inputs lol and lol 0 1 0 inputs lol and lor 0 1 1 inputs lir and lil 1 0 0 inputs lir and lir 1 0 1 inputs lil and lil 1 1 0 inputs lil and lir 1 1 1 table 12 switch setting at line out table 13 zero cross detection setting table 14 mute setting line out signals at data transmission status internal switch, readable bits: stp, sapp setting bits lol lor stereo sap sap sap sap received 1 1 mute mute no sap received 1 1 left right stereo received 1 0 mono mono no stereo received 1 0 mono sap sap received 0 1 mono mute no sap received 0 1 mono mono independent 0 0 function data tzcm direct mute control 0 mute control delayed until the next zero crossing 1 function data gmu function data lmu forced mute at outr, outl and outs 1 forced mute at lor and lol 1 audio processor controlled outputs 0 stereo processor controlled outputs 0
1997 mar 11 26 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 table 15 avl attack time table 16 adj bit setting table 17 avlon bit setting table 18 ccd bit setting table 19 sts bit setting (pilot threshold stereo on ) table 20 timing current setting function data at1 at2 r att = 420 w 00 r att = 730 w 10 r att = 1200 w 01 r att = 2100 w 11 function data stereo decoder operation mode 0 auto adjustment of channel separation 1 function data automatic volume control off 0 automatic volume control on 1 function data load current for normal avl decay time 0 increased load current 1 function data st on 35 mv 1 st on 30 mv 0 function i s range data tc2 tc1 tc0 +30% 1 0 0 +20% 1 0 1 +10% 1 1 0 nominal 0 1 1 - 10% 0 1 0 - 20% 0 0 1 - 30% 0 0 0 table 21 level adjust setting g l (db) data l3 l2 l1 l0 +4.0 1111 +3.5 1110 +3.0 1101 +2.5 1100 +2.0 1011 +1.5 1010 +1.0 1001 +0.5 1000 0.0 0111 - 0.5 0110 - 1.0 0101 - 1.5 0100 - 2.0 0011 - 2.5 0010 - 3.0 0001 - 3.5 0000
1997 mar 11 27 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 table 22 alignment data for expander in read register alr1 and alr2 and in write register ali1 and ali2 function data d4 ax4 d3 ax3 d2 ax2 d1 ax1 d0 ax0 gain increase 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 nominal gain 10000 01111 gain decrease 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000
1997 mar 11 28 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 table 23 explanation of curves in fig.4 curve capacitance at pin c ps1 (nf) capacitance at pin c ps2 (nf) effect 1 15 15 normal 2 5.6 47 intensi?ed 3 5.6 68 more intensi?ed fig.4 pseudo (phase in degrees) as a function of frequency (left output). (1) see table 23. (2) see table 23. (3) see table 23. handbook, full pagewidth - 400 0 (1) (2) (3) phase (degree) - 300 - 200 - 100 mha311 10 2 10 3 10 4 f (hz) 10 5 10
1997 mar 11 29 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 fig.5 automatic level control diagram. avl measured at pin eol/eor. y 1 axis output level in avl operation with typically 200 mv. y 2 axis v cav dc voltage at pin c av corresponds with typical gain steps in range of +6 to - 15 db. (1) v cav (2) v o max(rms) (3) v o min(rms) handbook, full pagewidth mha312 10 7 v cav (v) 6 5 4 3 2 1 1 v i(rms) (v) 10 - 1 300 250 200 160 10 - 2 100 v o(rms) (mv) (1) (2) (3) fig.6 volume control with loudness (including low roll-off frequency). handbook, full pagewidth - 35 - 25 - 15 - 5 25 16 14 9 4 - 1 - 6 - 11 - 16 - 21 - 26 - 31 - 36 v db (vqx 0) (db) mha313 10 2 10 10 3 f (hz) 10 4 5 15 parameter: volume gain setting (db)
1997 mar 11 30 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 internal pin configurations fig.7 pins outl, sol, sor and outr. 1 4.25 v 80 w mha314 + fig.8 pins ldl and ldr. 2 4.25 v 1.33 k w mha315 + fig.9 pins vil and vir. 3 4.25 v 10.58 k w 4.8 k w mha316 + fig.10 pins eol and eor. 4 4.25 v 15 k w mha317 6.8 k w + fig.11 pin c av . 5 mha318 + fig.12 pin v ref . 6 mha319 + 3.4 k w 3.4 k w
1997 mar 11 31 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 fig.13 pins lil and lir. 7 4.25 v 20 k w 20 k w mha320 + fig.14 pins avl and avr. 8 1 2 3 8 4.25 v 1.75 k w mha321 + fig.15 pins lol and lor. 10 4.25 v 5 k w mha322 + fig.16 pins c tw and c ts . 11 mha323 + fig.17 pins c w and c s . 13 6 k w mha324 + 4.25 v fig.18 pin veo. 15 mha325 +
1997 mar 11 32 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 fig.19 pin vei. 16 600 w mha326 + fig.20 pin c nr . 17 10 k w mha327 + 4.25 v fig.21 pin c m . 18 mha328 + fig.22 pin c dec . 19 4.25 v 20 k w 20 k w mha329 + fig.23 pin sda. 21 5 v 1.8 k w mha330 fig.24 pin scl. 22 5 v 1.8 k w mha331
1997 mar 11 33 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 fig.25 pin v cc . 23 + apply + 8.5 v to this pin mha332 fig.26 pin comp. 24 4.25 v 30 k w mha333 + fig.27 pin v cap . 25 4.7 k w 300 w 5 k w mha334 + fig.28 pin c p1 . 26 4.25 v 3.5 k w mha335 + fig.29 pin c p2 . 27 4.25 v 8.5 k w mha336 12 k w + fig.30 pin c ph . 28 4.25 v 10 k w 10 k w mha337 +
1997 mar 11 34 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 fig.31 pin c adj . 29 mha338 + fig.32 pin cer. 30 3 k w mha339 + fig.33 pins c mo and c ss . 31 4.25 v 10 k w 10 k w mha340 + fig.34 pins c ps1 and c ps2 . 38 15 k w mha341 +
1997 mar 11 35 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot270-1 90-02-13 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 3.2 2.9 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 42 1 22 21 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip42: plastic shrink dual in-line package; 42 leads (600 mil) sot270-1
1997 mar 11 36 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1997 mar 11 37 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). sdip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. qfp r eflow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary from 50 to 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheat for 45 minutes at 45 c. w ave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 mar 11 38 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 mar 11 39 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder and audio processor TDA9852 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2870, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 547047/1200/02/pp40 date of release: 1997 mar 11 document order number: 9397 750 01766

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